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Micro and Nanosystems

Editor-in-Chief

ISSN (Print): 1876-4029
ISSN (Online): 1876-4037

Research Article

Global RC Interconnects with ADL Buffers for Low-Power Applications

Author(s): Himani Bhardwaj*, Shruti Jain and Harsh Sohal

Volume 16, Issue 2, 2024

Published on: 17 May, 2024

Page: [112 - 122] Pages: 11

DOI: 10.2174/0118764029298466240508091306

Price: $65

Abstract

Introduction: Interconnects are an essential requirement for any circuit completion. They are utilised to connect two or more blocks, yet when creating a circuit, certain problems have been observed. Scaling back technology is one such problem.

Methods: With technology scaled down their aspects change which can straightforwardly affect the circuit boundaries. Because of this, the time constant and power consumption in the interconnect circuits has increased. Certain wire (RC) models and techniques have previously been characterized to control these performance parameters however in this paper, authors have proposed a new interconnect structure with a buffer insertion technique using adiabatic dynamic logic (ADL).

Results: To optimise power, a Schmitt trigger is inserted as a buffer between lengthy interconnect circuits utilising an energy-recovery mechanism. The TSPICE tool is used to model and simulate the entire circuit.

Conclusion: The suggested model's performance is compared to that of other cutting-edge methods.

Keywords: Interconnects, delay, power consumption, copper, VLSI, ADL buffers.

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